Embodiments of the inventive concept relate to a display controller for generating a video sync signal using an external clock, and more particularly, to a display controller for generating a video sync signal using an external clock, an application processor including the display controller, and an electronic system including the display controller.
A video sync signal must be supplied by a host device at a correct timing so that video data is properly transferred to a peripheral device and displayed. Accordingly, a clock used during the generation of the video sync signal typically has a tolerance of less than several hertz. A dedicated phase-locked loop (PLL) or fractional divider may be used to generate the clock.
However, when a dedicated PLL is used, continuous power consumption may occur while video data is being displayed and an overall chip size is increased, along with the area occupied by the dedicated PLL. When a fractional divider is used, an additional first-in first-out (FIFO) may be required, and constraints irrelevant to the performance of a clock may need to be dealt with.